`ifdef SIM
module sim_tb ();
    //iverilog -DSIM -f sim3.txt && vvp a.out
    reg clk = 0;
    reg rst_n = 0;
    reg memory_clk = 0;
    wire clk50m = clk;

    always clk = #10 ~clk;
    always memory_clk = #1.25 ~memory_clk;
    always rst_n = #100 1;
    always #140000 $finish;
    reg[31:0] counter = 0;

    localparam test_counter = 10;

    wire            sdio_clk;
    wire            sdio_cmd;
    wire [3:0]      sdio_dat;
    wire [3:0]      sdio_dat_no;

`define counter_cmp(cnt) (counter==test_counter+cnt||counter==test_counter+cnt+1)
`define counter_cmp_range(cnt1,cnt2)        ((counter>=cnt1) && (counter<=cnt2))
//`define TEST_WRITE

    always @(posedge clk) begin
        counter <= counter + 1;
        if(`counter_cmp(50))begin
            //重置命令
            //task_write(0,1<<10);
        end
    end

    sdModel u_sd(
        .sdClk (sdio_clk),
        .cmd(sdio_cmd),
        .dat({sdio_dat_no,sdio_dat})
    );

    ftsdc010_sim u_ftsdc010_sim(
        .sdio_clk       (sdio_clk)      ,
        .sdio_cmd       (sdio_cmd)      ,
        .sdio_dat       (sdio_dat)      ,
        .apb_psel       (apb_psel       ),
        .apb_addr       (apb_addr       ),
        .apb_pwdata     (apb_pwdata     ),
        .apb_prdata     (apb_prdata     ),
        .apb_pwrite     (apb_pwrite     ),
        .apb_ptran      (apb_ptran      ),
        .apb_pready_o   (apb_pready_o   ),
        .clk            (clk            ),
        .reset          (~rst_n         )
    );

    initial begin
        $dumpfile("test.vcd");
        $dumpvars(0, sim_tb);
    end
endmodule
`endif
